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ESS Technology, Inc.
DESCRIPTION
The ES6178 VibrattoS DVD processor is a super highperformance single-chip MPEG video decoding solution that provides not only DVD decoding, but also the emerging DivX and MPEG-4 support, allowing users to view video clips (from the Internet, a camcorder, or other source) on DVD players. The ES6178 integrates a state-of-the-art progressivescan video feature to provide brilliant and sharp, flickerfree output to the video display, built-in CPRM, and S/PDIF input and output support. The ES6178 perfor ms audio/video stream data processing, TV encoding, Macrovision copy protection, DVD system navigation, system control, and housekeeping functions. The Vibratto-S DVD processor is built on the ESS proprietar y dual CPU Programmable Multimedia Processor (PMP) core consisting of 32-bit RISC and 64-bit DSP processors and offers the best DVD feature set. The processing units enable simultaneous parallel execution of system commands and data processing to perform specialized encoding and decoding tasks. The RISC processor performs bit stream parsing, control audio data output, transfer video and audio data to the vector engine and service system control and housekeeping functions. The vector engine performs audio and video micro-code processing required by A/V standards, such as Dolby Digital, MPEG and JPEG imaging. These processing tasks include video motion compensation and estimation, loop filtering, Discrete Cosine Transforms (DCT), inverse DCT, quantization, and inverse quantization. The Vibratto-S DVD processor supports both parallel and serial DVD loader interfaces, industry standard I2S audio data input and output, EPROM and DRAM access, and audio/video data buffering. It also supports both letterbox and pan-and-scan displays, sub-picture overlay, and OnScreen Display (OSD). In addition, the Vibratto-S DVD solution plays Karaoke, CD+G, DVD-Audio, HDCD, CDDA, MP3, and WMA. The ES6178 processor is available in a 208-pin Plastic Quad Flat Pack (PQFP) device package.
ES6178 Vibratto-S DVD Processor Product Brief
FEATURES
* Single-chip DVD processor. * DivX and MPEG-4 Advanced Simple Profile* at full
screen (D1). * Integrated NTSC/PAL encoder with pixel-adaptive de-interlacer and five 10-bit 54 MHz video DACs. * High-quality progressive scan video output for flicker-free video display. * DVD-Video, DVD-VR, VCD 1.1 and 2.0, and SVCD.
* Full DVD-Audio support including MLP and LPCM
decode, CPPM decryption, and watermark detection.
* Media playback with CD-ROM, CD-R/RW, DVD-R/RW,
DVD+R/RW, and DVD-RAM. * Up to 7.1 channel audio outputs.
* * * *
Interface for IDE devices and A/V DVD loaders. Interface for CF, MS, SD, MMC, and SD memory cards. Direct interface of 8-/16-bit DRAM up to 128-Mb capacity.
Direct interface for up to 4 banks of 8-/16-bit EPROM or Flash EPROM for up to 4-MB for each bank. * Macrovision 7.1 for NTSC/PAL interlaced video.
* Macrovision NTSC/PAL (480p/576p) progressive scan
video.
* Simultaneous composite, S-video, and YUV outputs. * CCIR 656/601 YUV 4:2:2 input and output. * On-Screen Display controller supports 256 colors in 8
degrees of transparency. * Subpicture Unit (SPU) decoder supports karaoke lyric, subtitles, and EIA-608 compliant Line 21 Captioning. * SmartLogo for custom JPEG wallpaper.
* JPEG digital photo support (Kodak Picture CD and * * * * * * * * * *
Fujifilm FujiColor CD). ESS Music SlideshowTM. Bass management. Dolby Digital (AC-3), Dolby Pro LogicTM, and Pro Logic II. DTS surround. S/PDIF digital audio input and output. MPEG AAC and Multichannel. SRS TruSurround and TruSurround XT. WindowsTM Media Audio decoding. Professional karaoke with full scoring scheme. Lead-free leads using 98%-Sn/2%-Cu or 98%-Sn/2%-Bi available with ES6178FF.
ESS Technology, Inc.
SAM0527-052705
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2
VEE HA2/AUX4[4] VEE I2CDATA/AUX0 I2C_CLK/AUX1 AUX2/IOW# VSS VEE AUX3/IOR# AUX4 AUX5 AUX6 AUX7 LOE# VSS VCC LCS0#/PIXOUT_CLK LCS1# LCS2# LCS3# VSS LD0 LD1 LD2 LD3 LD4 VEE VSS LD5 LD6 LD7 LD8 LD9 LD10 LD11 VSS VEE LD12 LD13 LD14 LD15 LWRLL# LWRHL# VSS VEE CAMIN0/PIXIN0 CAMIN1/PIXIN1 LA0 LA1 LA2 LA3 VSS 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
ES6178 PINOUT DIAGRAM
The device pinout for the ES6178 is shown in Figure 1.
SAM0527-052705
ES6178
Figure 1 ES6178 Device Pinout
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 VEE VSS DSCK DQM DCS0# VEE VSS DCS1# DB15 DB14 DB13 DB12 VEE VSS DB11 DB10 DB9 DB8 DB7 DB6 VSS VCC DB5 DB4 DB3 DB2 DB1 DB0 VSS VEE DMBS1 DMBS0 DRAS# DWE# DOE#/DSCK_EN DCAS# VEE VSS DMA11 DMA10 DMA9 DMA8 DMA7 DMA6 VSS VEE DMA5 DMA4 DMA3 DMA2 DMA1 DMA0
VEE LA4 LA5 LA6 LA7 LA8 LA9 VSS VCC LA10 LA11 LA12 LA13 LA14 LA15 LA16 VSS VEE LA17 LA18 LA19 LA20 LA21 RESET# TDMDX/RSEL VSS VEE TDMDR TDMCLK TDMFS TDMTSC# TWS/SEL_PLL2 TSD0/SEL_PLL0 VSS VCC TSD1/SEL_PLL1 TSD2 TSD3 MCLK TBCK SEL_PLL3/SPDIF_OUT SPDIF_IN VSS VCC RSD RWS RBCK CAMIN3/PIXIN3 XIN XOUT AVEE AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
VSS HA1/AUX4[3] HA0/AUX4[2] HCS3FX#/AUX3[6] HCS1FX#/AUX3[7] HIOCS16#/AUX3[4]/CAMCLK/PIXIN_CLK HRD#/DCI_ACK#/AUX4[6] HWR#/DCI_CLK/AUX4[5] VEE VSS HIORDY/AUX3[3] HRST#/AUX3[5] HIRQ/DCI_ERR#/AUX4[7] HRRQ#/AUX4[0]/CAMIN2/PIXIN2 HWRQ#/DCI_REQ#/AUX4[1] HD15/AUX2[7]/IR HD14/AUX2[6] VCC VSS HD13/AUX2[5]/SP HD12/AUX2[4]/C2PO HD11/AUX2[3]//IRQ HD10/AUX2[2] HD9/AUX2[1] HD8/DCI_FDS#/AUX2[0]/VFD_CLK HD7/DCI7/AUX1[7]/VFD_DIN VEE VSS HD6/DCI6/AUX1[6]/VFD_DOUT HD5/DCI5/AUX1[5] HD4/DCI4/AUX1[4] HD3/DCI3/AUX1[3] HD2/DCI2/AUX1[2] HD1/DCI1/AUX1[1] HD0/DCI0/AUX1[0] VCC VSS HSYNC#/AUX3[0]/CAMIN7/PIXIN7 VSYNC#/AUX3[1]/CAMIN6/PIXIN6 PCLKQSCN/AUX3[2]/CAMIN5/PIXIN5 PCLK2XSCN/CAMIN4/PIXIN4 FDAC/YUV7/PIXOUT7 VDAC/YUV6/PIXOUT6 YDAC/YUV5/PIXOUT5 ADVSS ADVEE RSET/YUV4/PIXOUT4 COMP/YUV3/PIXOUT3 CDAC/YUV2/PIXOUT2 VREF/YUV1/PIXOUT1 UDAC/YUV0/PIXOUT0 DCLK
ES6178 PRODUCT BRIEF
ES6178 PINOUT DIAGRAM
ESS Technology, Inc.
ES6178 PRODUCT BRIEF ES6178 PIN DESCRIPTION
ES6178 PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES6178. Table 1 Name VEE ES6178 Pin Description Pin Numbers 1,18, 27, 59, 68, 75, 92, 99, 104, 130, 148, 157, 159, 164, 183, 193, 201 2-7, 10-16, 19-23, 204-207 8, 17, 26, 34, 43, 60, 67, 76, 84, 91, 98, 103, 120, 129, 138, 147, 156, 163, 171, 177, 184, 192, 200, 208 9, 35, 44, 83, 121, 139, 172 24 I/O Definition
P
I/O power supply.
LA[21:0] VSS
O
RISC port address bus.
G
Ground.
VCC RESET# TDMDX RSEL
P I O I
Core power supply. Reset input; (5V tolerant input). TDM transmit data output. LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-k resistor; read only during reset. RSEL 0 1 Selection 16-bit ROM 8-bit ROM
25
TDMDR TDMCLK TDMFS TDMTSC# TWS SEL_PLL2
28 29 30 31
I I I O O I
TDM receive data input; (5V tolerant input). TDM clock input; (5V tolerant input). TDM frame sync input; (5V tolerant input). TDM output enable. Audio transmit frame sync output. System and DSCK output clock frequency selection is made at the rising edge of RESET#. The matrix below lists the available clock frequencies and their respective PLL bit settings. Strapped to VCC or ground via 4.7-k resistor; read only during reset. SEL_PLL2 0 SEL_PLL1 0 0 1 1 0 0 1 1 SEL_PLL0 0 1 0 1 0 1 0 1 PLL Settings DCLK x 4.5 DCLK x 5.0 Bypass DCLK x 4.0 DCLK x 4.25 DCLK x 4.75 DCLK x 5.5 DCLK x 6.0
32
0 0 0 1 1 1 1
TSD0 33 SEL_PLL0 ESS Technology, Inc.
O I
Audio transmit serial data output 0. Refer to the description and matrix for SEL_PLL2 pin 32. SAM0527-052705 3
ES6178 PRODUCT BRIEF ES6178 PIN DESCRIPTION Table 1 Name TSD1 36 SEL_PLL1 TSD2 TSD3 MCLK TBCK SEL_PLL3 37 38 39 40 I O O I/O I/O I Refer to the description and matrix for SEL_PLL2 pin 32. Audio transmit serial data output 2. This pin must be pulled down to VSS via a 4.7-k resistor for proper operation. Audio transmit serial data output 3. Audio master clock for audio DAC. Audio transmit bit clock. TBCK is an input during reset and subsequently is programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4). Clock source select. Strapped to VCC or ground via 4.7-k resistor; read only during reset. SEL_PLL3 41 0 1 SPDIF_OUT SPDIF_IN RSD RWS RBCK CAMIN3 48 PIXIN3 XIN XOUT AVEE AVSS DMA[11:0] DCAS# DOE# 70 DSCK_EN DWE# DRAS# DMBS0 DMBS1 DB[15:0] DCS[1:0]# DQM DSCK DCLK 4 71 72 73 74 77-82, 85-90, 93-96 97,100 101 102 105 SAM0527-052705 O O O O O I/O O O O I DRAM clock enable. DRAM write enable. DRAM row address strobe. DRAM bank select 0. DRAM bank select 1. DRAM data bus. DRAM chip select. Data input/output mask. Output clock to DRAM. Clock input to PLL; (5V tolerant input). ESS Technology, Inc. 49 50 51 52 53-58, 61-66 69 I I O P G O O O CCIR656 input pixel 3. 27-MHz crystal input. 27-MHz crystal output. Analog power for PLL. Analog ground for PLL. DRAM address bus. DRAM column address strobe. DRAM output enable. 42 45 46 47 O I I I I I S/PDIF output. S/PDIF input; (5V tolerant input). Audio receive serial data; (5V tolerant input). Audio receive frame sync; (5V tolerant input). Audio receive bit clock; (5V tolerant input). Camera YUV 3. Clock Source Crystal oscillator DCLK input ES6178 Pin Description (Continued) Pin Numbers I/O O Definition Audio transmit serial data output 1.
ES6178 PRODUCT BRIEF ES6178 PIN DESCRIPTION Table 1 Name UDAC ES6178 Pin Description (Continued) Pin Numbers I/O Definition Video DAC output. Value 0 1 2 3 4 5 6 O 106 7 8 9 10 11 12 13 14 F DAC (pin 115) CVBS/Chroma CVBS/Chroma CVBS/Chroma CVBS/Chroma CVBS/Chroma CVBS/Chroma CVBS/Chroma N/A CVBS/Chroma CVBS CVBS N/A CVBS/Chroma CVBS/Chroma Chroma V DAC (pin 114) CVBS1 CVBS1 N/A CVBS1 CVBS1 CVBS1 N/A SYNC Chroma CVBS1 CVBS1 SYNC N/A CVBS1 Y Y DAC C DAC U DAC (pin 113) (pin 108) (pin 106) Y Y Y N/A N/A Y Y G Y G G G Y Y G C C C N/A N/A Pb Pb B Pb B R R Pr Pr R N/A CVBS2 N/A CVBS2 N/A Pr Pr R Pr R B B Pb Pb B
F: CVBS/chroma signal for simultaneous mode. Y: Luma component for YUV and Y/C processing. C: Chrominance signal for Y/C processing. U: Chrominance component signal for YUV mode. V: Chrominance component signal for YUV mode. YUV0 PIXOUT0 VREF YUV1 PIXOUT1 CDAC YUV2 PIXOUT2 COMP YUV3 PIXOUT3 RSET YUV4 PIXOUT4 ADVEE ESS Technology, Inc. 111 110 109 108 107 O O I O O O O O I O O I O O P YUV pixel 0 output data. CCIR656 output pixel 0. Internal voltage reference to video DAC. Bypass to ground with 0.1-F capacitor. YUV pixel 1 output data. CCIR656 output pixel 1. Video DAC output. Refer to description and matrix for UDAC pin 106. YUV pixel 2 output data. CCIR656 output pixel 2. Compensation input. Bypass to ADVEE with 0.1-F capacitor. YUV pixel 3 output data. CCIR656 output pixel 3. DAC current adjustment resistor input. YUV pixel 4 output data. CCIR656 output pixel 4. Analog power for video DAC. SAM0527-052705 5
ES6178 PRODUCT BRIEF ES6178 PIN DESCRIPTION Table 1 Name ADVSS YDAC YUV5 PIXOUT5 VDAC YUV6 PIXOUT6 FDAC YUV7 PIXOUT7 PCLK2XSCN CAMIN4 PIXIN4 PCLKQSCN AUX3[2] 117 CAMIN5 PIXIN5 VSYNC# AUX3[1] 118 CAMIN6 PIXIN6 HSYNC# AUX3[0] 119 CAMIN7 PIXIN7 HD[5:0] DCI[5:0] AUX1[5:0] HD6 DCI6 128 AUX1[6] VFD_DOUT HD7 DCI7 131 AUX1[7] VFD_DIN I/O I Aux1 data I/O; (5V tolerant input). VFD data input. I/O I I/O I/O Aux1 data I/O; (5V tolerant input). VFD data output. Host data bus line; (5V tolerant input). DVD channel data I/O; (5V tolerant input). 122-127 I I I/O I/O I/O I/O I/O Camera YUV 7. CCIR656 input pixel 7. Host data bus lines; (5V tolerant input). DVD channel data I/O; (5V tolerant input). Aux1 data I/O; (5V tolerant input). Host data bus line; (5V tolerant input). DVD channel data I/O; (5V tolerant input). I I I/O I/O Camera YUV 6. CCIR656 input pixel 6. Horizontal sync; (5V tolerant input). Aux3 data I/O; (5V tolerant input). I I I/O I/O Camera YUV 5. CCIR656 input pixel 5. Vertical sync; (5V tolerant input). Aux3 data I/O; (5V tolerant input). 116 115 114 113 ES6178 Pin Description (Continued) Pin Numbers 112 I/O G O O O O O O O O O I/O I I O I/O Definition Analog ground for video DAC. Video DAC output. Refer to description and matrix for UDAC pin 106. YUV pixel 5 output data CCIR656 output pixel 5. Video DAC output. Refer to description and matrix for UDAC pin 106. YUV pixel 6 output data. CCIR656 output pixel 6. Video DAC output. Refer to description and matrix for UDAC pin 106. YUV pixel 7 output data. CCIR656 output pixel 7. 27-MHz video output pixel clock. Camera YUV 4. CCIR656 input pixel 4. 13.5-MHz video output pixel clock. Aux3 data I/O; (5V tolerant input).
6
SAM0527-052705
ESS Technology, Inc.
ES6178 PRODUCT BRIEF ES6178 PIN DESCRIPTION Table 1 Name HD8 DCI_FDS# 132 AUX2[0] VFD_CLK HD9 133 AUX2[1] HD10 134 AUX2[2] HD11 AUX2[3] IRQ HD12 AUX2[4] C2PO HD13 AUX2[5] SP HD14 140 AUX2[6] HD15 AUX2[7] IR HWRQ# DCI_REQ# AUX4[1] HRRQ# AUX4[0] 143 CAMIN2 PIXIN2 HIRQ DCI_ERR# AUX4[7] HRST# 145 AUX3[5] HIORDY 146 AUX3[3] I/O Aux3 data I/O; (5V tolerant input). I/O I Aux3 data I/O; (5V tolerant input). Host I/O ready. 144 I I I/O I/O I/O O Camera YUV 2. CCIR656 input pixel 2. Host interrupt. DVD channel data error; (5V tolerant input). Aux4 data I/O; (5V tolerant input). Host reset. 142 141 I/O I/O I/O I O O I/O O I/O Aux2 data I/O; (5V tolerant input). Host data bus line; (5V tolerant input). Aux2 data I/O; (5V tolerant input). IR remote control input; (5V tolerant input). Host write request. DVD control interface request. Aux4 data I/O; (5V tolerant input). Host read request. Aux4 data I/O; (5V tolerant input). 137 136 135 I/O I/O I/O O I/O I/O I I/O I/O I I/O Aux2 data I/O; (5V tolerant input). Host data bus line; (5V tolerant input). Aux2 data I/O; (5V tolerant input). IRQ. Host data bus line; (5V tolerant input). Aux2 data I/O; (5V tolerant input). C2PO error correction flag from CD-ROM; (5V tolerant input). Host data bus line; (5V tolerant input). Aux2 data I/O; (5V tolerant input). 16550 UART serial port input. Host data bus line; (5V tolerant input). I/O I/O Aux2 data I/O; (5V tolerant input). Host data bus line; (5V tolerant input). I/O I I/O Aux2 data I/O; (5V tolerant input). VFD clock input. Host data bus line; (5V tolerant input). ES6178 Pin Description (Continued) Pin Numbers I/O I/O I/O Definition Host data bus line; (5V tolerant input). DVD input sector start; (5V tolerant input).
ESS Technology, Inc.
SAM0527-052705
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ES6178 PRODUCT BRIEF ES6178 PIN DESCRIPTION Table 1 Name HWR# DCI_CLK AUX4[5] HRD# DCI_ACK# AUX4[6] HIOCS16# AUX3[4] 151 CAMCLK PIXIN_CLK HCS1FX# 152 AUX3[7] HCS3FX# 153 AUX3[6] HA[2:0] 154, 155, 158 AUX4[4:2] AUX0 160 I2CDATA AUX1 161 I2C_CLK AUX2 162 IOW# AUX3 165 IOR# AUX4-7 LOE# LCS0# 173 PIXOUT_CLK LCS[3:1]# LD[15:0] LWRLL# LWRHL# CAMIN0 202 PIXIN0 CAMIN1 203 PIXIN1 I CCIR656 input pixel 1. I I CCIR656 input pixel 0. Camera YUV 1. 174-176 178-182, 185-191, 194-197 198 199 O O I/O O O I CCIR656 output pixel clock. RISC port chip select [3:1]. RISC port data bus; (5V tolerant input). RISC port low-byte write enable. RISC port high-byte write enable. Camera YUV 0. 166-169 170 O I/O O O I/O read strobe (LCS1). Auxiliary ports; (5V tolerant input). RISC port output enable. RISC port chip select 0. O I/O I/O write strobe (LCS1). Auxiliary port; (5V tolerant input). I/O I/O I2C clock I/O; (5V tolerant input). Auxiliary port; (5V tolerant input). I/O I/O I2C data I/O; (5V tolerant input). Auxiliary port 1 (open collector); (5V tolerant input). I/O I/O Aux4 data I/Os; (5V tolerant input). Auxiliary port 0 (open collector); (5V tolerant input). I/O I/O Aux3 data I/O; (5V tolerant input). Host address bus. I/O O Aux3 data I/O; (5V tolerant input). Host select 3. I I O Camera port pixel clock input. CCIR656 input pixel clock. Host select 1. 150 149 ES6178 Pin Description (Continued) Pin Numbers I/O I/O I/O I/O O I/O I/O I I/O Definition Host write. DVD channel data clock; (5V tolerant input). Aux4 data I/O; (5V tolerant input). Host read. DVD channel data valid; (5V tolerant input). Aux4 data I/O; (5V tolerant input). Device 16-bit data transfer. Aux3 data I/O; (5V tolerant input).
8
SAM0527-052705
ESS Technology, Inc.
ES6178 PRODUCT BRIEF SYSTEM BLOCK DIAGRAM
SYSTEM BLOCK DIAGRAM
A sample system block diagram for the ES6178 Vibratto-S DVD player board design is shown in Figure 2.
Analog Video ROM/Flash Digital Video (CCIR656/601)
TV Display Digital Devices
SDRAM (4/16 MB)
Audio DAC
Speakers A/V Receiver Microphone In VFD Panel IR Remote
EEPROM
ES6178 Vibratto-S
S/PDIF Audio ADC
DVD Drive
VFD Driver
Figure 2 ES6178 Vibratto-S System Block Diagram
FUNCTIONAL DESCRIPTION
Figure 3 shows the internal block diagram for the ES6178 Vibratto-S DVD processor.
GPIO
SRAM/ROM Interface
32-Bit RISC Processor 16 K Cache
OSD Display Subpicture Controller
TV-Encoder
TDM Interface
CCIR656/601 Output Interface
Gateway +
DCI Interface
DVD Descrambler + Transport
DMA Controller
Huffman Decoder Host Interface
DRAM Interface
Video Processor CCIR656/601 Input Interface
ROM
Serial Audio Interface
RAM
Figure 3 ES6178 Vibratto-S Block Diagram ESS Technology, Inc. SAM0527-052705 9
ES6178 PRODUCT BRIEF ORDERING INFORMATION
ORDERING INFORMATION
Part Number ES6178F ES6178FF Description Vibratto-S DVD, Progressive scan, DivX (certified), DVD-Audio, and TV encoder Vibratto-S DVD, Progressive scan, DivX (certified), DVD-Audio, and TV encoder with lead-free leads Package 208-pin PQFP 208-pin PQFP
The letter F at the end of the ordering part number identifies the package type PQFP. The second letter F indicates lead-free leads with the device.
Other Vibratto-S DVD Processors
Part Number ES6128F ES6128FF ES6168FA ES6168FAF Description Vibratto-S DVD, Progressive scan, and TV Encoder Vibratto-S DVD, Progressive scan, and TV Encoder with lead-free leads Vibratto-S DVD, Progressive scan, MPEG-4, DVD-Audio, and TV encoder Vibratto-S DVD, Progressive scan, MPEG-4, DVD-Audio, and TV encoder with lead-free leads Package 208-pin PQFP 208-pin PQFP 208-pin PQFP 208-pin PQFP
The letter F at the end of the ordering part number identifies the package type PQFP. The second letter F indicates lead-free leads with the device.
No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc.
MPEG is the Moving Picture Experts Group of the ISO/IEC. References to MPEG in this document refer to the ISO/IEC JTC1 SC29 committee draft ISO 11172 dated January 9, 1992. Vibratto, SmartBright, SmartLogo, SmartColor, and Music Slideshow are trademarks of ESS Technology, Inc. Dolby is a trademark of Dolby Laboratories, Inc. Trusurround, Trusurround XT, SRS, and (o) symbol are trademarks of SRS Labs., Inc. All other trademarks are trademarks of their respective companies and are used for identification purposes only.
ESS Technology, Inc. 48401 Fremont Blvd. Fremont, CA 94538 Tel: (510) 492-1088 Fax: (510) 492-1898
10 http://www.esstech.com
ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications are subject to change without prior notice. ESS Technology, Inc. assumes no responsibility for any errors contained herein. U.S. patents pending.
(c) 2005 ESS Technology, Inc.
SAM0527-052705

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